As the size of microelectronic devices continues to decrease, the space or pitch between external attachment structures, such as solder bumps, for the microelectronic devices becomes smaller. As a result, the tolerances for the processes become smaller. These processes may include photolithography, used in forming the external attachment structures and their related structures within the microelectronic device. The processes may also include the formation of dielectric layers and the application of metal conductive traces. The external mounting elements, such as motherboard connection pads also become smaller and smaller and must be applied more precisely. These smaller tolerances increase the potential of misalignment, which may result in reliability issues and yield loss for the microelectronic devices.
In photolithography the alignment between different layers of a package substrate must have increasing precision for package substrate manufacturing. Layers such as solder resist layers must be aligned to Cu layers, and ABF layers to Cu layers.
Similarly with such package substrate connections, the quality of the solder joint affects the reliability of the package. Current tests for solder joint reliability are imprecise or require that the device being tested be destroyed.